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features floating channel designed for bootstrap operation fully operational to +600 v tolerant to negative transient voltage, dv/dt immune gate drive supply range from 10 v to 20 v undervoltage lockout for both channels cmos schmitt-triggered inputs with pull-down matched propagation delay for both channels internally set deadtime high-side output in phase with input rohs compliant typical connection data sheet no. pd60253 half-bridge driver product summary v offset 600 v max. i o +/- 200 ma / 420 ma v out 10 v - 20 v t on/off (typ.) 750 ns & 150 ns deadtime (typ.) 650 ns www.irf.com 1 irs2111 ( s ) pbf v cc v b v s ho lo in com in up to 600 v to load v cc (refer to lead assignments for correct pin configuration). this diagram shows electrical connections only. please refer to our application notes and designtips for proper circuit board layout. description the irs2111 is a high voltage, high speed power mosfet and igbt driver with dependent high-side and low-side referenced output channels designed for half-bridge applications. propri- etary hvic and latch immune cmos technologies enable ruggedized monolithic construction. logic input is compatible with standard cmos outputs. the output drivers feature a high pulse current buffer stage designed for minimum driver cross- conduction. internal deadtime is provided to avoid shoot-through in the output half-bridge. the floating channel can be used to drive an n-channel power mosfet or igbt in the high-side con- figuration which operates up to 600 v. packages 8-lead pdip irs2111pbf 8-lead soic irs21111spbf
irs2111(s)pbf www.irf.com 2 symbol definition min. max. units v b high-side floating supply voltage -0.3 625 (note 1) v s high-side floating supply offset voltage v b - 25 v b + 0.3 v ho high-side floating output voltage v s - 0.3 v b + 0.3 v cc low-side and logic fixed supply voltage -0.3 25 (note 1) v lo low-side output voltage -0.3 v cc + 0.3 v in logic input voltage -0.3 v cc + 0.3 dv s /dt allowable offset supply voltage transient (fig. 2) ? 50 v/ns p d package power dissipation @ t a +25 c (8 le ad pdip) ? 1.0 (8 lead soic) ? 0.625 rth ja thermal resistance, junction to ambient (8 lead pdip) ? 125 (8 lead soic) ? 200 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. additional information is shown in figs. 7 through 10. v w c/w c symbol definition min. max. units v b high-side floating supply absolute voltage v s + 10 v s + 20 v s high-side floating supply offset voltage note 2 600 v ho high-side floating output voltage v s v b v cc low-side and logic fixed supply voltage 10 20 v lo low-side output voltage 0 v cc v in logic input voltage 0 v cc t a ambient temperature -40 125 note 2: logic operational for v s of -5 v to +600 v. logic state held for v s of -5 v to -v bs . (please refer to the design tip dt97-3 for more details). recommended operating conditions the input/output logic timing diagram is shown in fig. 1. for proper operation the device should be used within the recommended conditions. the v s offset rating is tested with all supplies biased at a 15 v differential. c v note 1: all supplies are fully tested at 25 v, and an internal 20 v clamp exists for each supply
irs2111(s)pbf www.irf.com 3 symbol definition min. typ.max.unitstest conditions 6.4 ? ? v cc = 10 v v ih logic ?1? input voltage for ho & logic ?0? for lo 9.5 ? ? v cc = 15 v 12.6 ? ? v cc = 20 v ? ? 3.8 v cc = 10 v v il logic ?0? input voltage for ho & logic ?1? for lo ? ? 6.0 v cc = 15 v ? ? 8.3 v cc = 20 v v oh high level output voltage, v bias - v o ? 0.05 0.2 v ol low level output voltage, v o ? 0.02 0.1 i lk offset supply leakage current ? ? 50 v b = v s = 600 v i qbs quiescent v bs supply current ? 50 100 i qcc quiescent v cc supply current ? 70 180 i in+ logic ?1? input bias current ? 30 50 v in = v cc i in- logic ?0? input bias current ? ? 5.0 v in = 0 v v bsuv+ v bs supply undervoltage positive going threshold 7.6 8.6 9.6 v bsuv- v bs supply undervoltage negative going threshold 7.2 8.2 9.2 v ccuv+ v cc supply undervoltage positive going threshold 7.6 8.6 9.6 v ccuv- v cc supply undervoltage negative going threshold 7.2 8.2 9.2 i o+ output high short circuit pulsed current 200 290 ? v o = 0 v, v in = v cc pw 10 s i o- output low short circuit pulsed current 420 600 ? v o = 15 v, v in = 0 v pw 10 s static electrical characteristics v bias (v cc , v bs ) = 15 v and t a = 25 c unless otherwise specified. the v in , v th, and i in parameters are referenced to com. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. ma v v a symbol definition min. typ.max.unitstest conditions t on turn-on propagation delay 550 750 950 v s = 0 v t off turn-off propagation delay ? 150 180 v s = 600 v t r turn-on rise time ? 75 130 t f turn-off fall time ? 35 65 dt deadtime, ls turn-off to hs turn-on & 480 650 820 hs turn-off to ls turn-on mt delay matching, hs & ls turn-on/off ? 30 ? dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, c l = 1000 pf and t a = 25 c unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in fig. 3. ns v in = 0 v or v cc i o = 2 ma
irs2111(s)pbf www.irf.com 4 symbol description inlogic input for high- side and low- side gate driver outputs (ho & lo), in phase with ho v b high- side floating supply hohigh- side gate drive output v s high- side floating supply return v cc low- side and logic fixed supply lolow- side gate drive output comlow- side return functional block diagram 8 lead dip 8 lead soic irs2111 irs2111s part number lead assignments lead definitions pulse gen in uv detect com ho v s v cc lo v b q s r r pulse filter hv level shift dead time dead time uv detect
irs2111(s)pbf www.irf.com 5 figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 5. deadtime waveform definitions figure 6. delay matching waveform definitions
irs2111(s)pbf www.irf.com 6 0 50 100 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 t u r n - o f f d e l a y t i m e ( n s ) ) temperature (c) 0 50 100 150 200 250 300 350 400 10 12 14 16 18 20 t u r n - o f f d e l a y t i m e ( n s ) ) v bias supply voltage (v) 0 50 100 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 temperature (c) 0 50 100 150 200 250 300 350 400 10 12 14 16 18 20 v bias supply voltage (v) figure 7b turn-on time vs voltage figure 8a turn-off time vs temperature figure 7a turn-on time vs temperature figure 8b turn-off time vs voltage figure 9a turn-on rise time vs temperature figure 9b turn-on rise time vs voltage max typ max typ max typ max typ 0 250 500 750 1000 1250 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) typ. max. min. 0 250 500 750 1000 1250 1500 10 12 14 16 18 20 v bias supply voltage (v) typ. max. min. t u r n - o n d e l a y t i m e ( n s ) t u r n - o n d e l a y t i m e ( n s ) t u r n - o n r i s e t i m e ( n s ) t u r n - o n r i s e t i m e ( n s )
irs2111(s)pbf www.irf.com 7 0 50 100 150 200 -50 -25 0 25 50 75 100 125 temperature (c) figure 10a turn-off fall time vs temperature 0 50 100 150 200 10 12 14 16 18 20 v bias supply voltage (v) 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature 0 3 6 9 1 2 1 5 10 12 14 16 18 20 min figure 10b turn-off fall time vs voltage figure 11a deadtime vs temperature figure 11b deadtime vs voltage figure 12a logic ?i? input voltage for ho & logic ?0? for lo vs temperature figure 12b logic ?i? input voltage for ho & logic ?0? for lo vs voltage max typ max typ min 0 250 500 750 1000 1250 -50 -25 0 25 50 75 100 125 temperature ( o c) typ. max. min. 0 250 500 750 1000 1250 10 12 14 16 18 20 v bias supply voltage (v) d e a d t i m e ( n s ) typ. max. min. t u r n - o f f f a l l t i m e ( n s ) t u r n - o f f f a l l t i m e ( n s ) d e a d t i m e ( n s ) l o g i c ? 1 ? i n p u t t h r e s h o l d ( v ) l o g i c ? 1 ? i n p u t t h r e s h o l d ( v ) v bias supply voltage
irs2111(s)pbf www.irf.com 8 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v cc supply voltage (v) l o w l e v e l o u t p u t v o l t a g e ( v ) 0.0 0.2 0.4 0.6 0.8 1.0 10 12 14 16 18 20 v cc supply voltage (v) h i g h l e v e l o u t p u t v o l t a g e ( v ) figure 14b. high level output vs. supply voltage 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature ( o c) h i g h l e v e l o u t p u t v o l t a g e ( v ) figure 14a. high level output vs. temperature figure 15a. low level output vs. temperature figure 13a logic ?0? input voltage for ho & logic ?i? for lo vs temperature figure 13b logic ?0? input voltage for ho & logic ?i? for lo vs voltage 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature max 0 3 6 9 1 2 1 5 10 12 14 16 18 20 v cc logic supply voltage (v) max max. figure 15b. low level output vs. voltage l o g i c ? 0 ? i n p u t t h r e s h o l d ( v ) l o g i c ? 0 ? i n p u t t h r e s h o l d ( v ) max. typ. max. typ. 0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) l o w l e v e l o u t p u t v o l t a g e ( v ) max. typ. typ.
irs2111(s)pbf www.irf.com 9 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max. temperature (c) figure 16b offset supply current vs voltage figure 16a offset supply current vs temperature 0 50 100 150 200 -50 -25 0 25 50 75 100 125 max. typ . temperature (c) 0 50 100 150 200 10 12 14 16 18 20 max. typ . v bs floating supply voltage (v) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 typ max temperature (c) figure 17a v bs supply current vs temperature figure 17b v bs supply current vs voltage figure 18a v cc supply current vs temperature figure 18b v cc supply current vs voltage 0 100 200 300 400 500 10 12 14 16 18 20 v cc fixed supply voltage (v) max typ o f f s e t s u p p l y c u r r e n t ( m a ) o f f s e t s u p p l y c u r r e n t ( m a ) v b s s u p p l y c u r r e n t ( m a ) v b s s u p p l y c u r r e n t ( m a ) v c c s u p p l y c u r r e n t ( m a ) v c c s u p p l y c u r r e n t ( m a ) 0 100 200 300 400 500 0 0 100 200 300 400 500 600 0 100 200 300 400 500 max. v b boost voltage (v)
irs2111(s)pbf www.irf.com 10 figure 19b logic ?1? input current vs. v cc voltage figure 20b. logic ?0? input bias current vs. v cc voltage figure 19a logic ?1? input current vs. temperature 0 20 40 60 80 100 120 -50 -25 0 25 50 75 100 125 temperature (c) 0 20 40 60 80 100 120 10 12 14 16 18 20 typ . max. figure 21 v bs undervoltage threshold (+) vs. temperature figure 22 v bs undervoltage threshold (-) vs. temperature l o g i c ? 1 ? i n p u t b i a s c u r r e n t ( m a ) l o g i c ? 1 ? i n p u t b i a s c u r r e n t ( m a ) 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 v b s u v l o t h r e s h o l d + ( v ) temperature (c) min. typ. max . 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 v b s u v l o t h r e s h o l d - ( v ) temperature (c ) min . typ. max . l o g i c ? 0 ? i n p u t b i a s c u r r e n t ( m a ) max. typ. max 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature (c) l o g i c " 0 " i n p u t b i a s c u r r e n t ( a ) l o g i c ? 0 ? i n p u t b i a s c u r r e n t ( m a ) figure 20a. logic "0" input bias current vs. temperature max 0 1 2 3 4 5 6 10 12 14 16 18 20 supply voltage (v) figure 20b. logic "0" input bias current v cc supply voltage (v)
irs2111(s)pbf www.irf.com 11 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) o u t p u t s o u r c e c u r r e n t ( m a ) ( m a ) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) o u t p u t s o u r c e c u r r e n t ( m a ) ( m a ) 0 150 300 450 600 750 900 10 12 14 16 18 20 v bias supply voltage (v) o u t p u t s i n k c u r r e n t ( m a ) ( m a ) 0 150 300 450 600 750 900 -50 -25 0 25 50 75 100 125 temperature ( o c) o u t p u t s i n k c u r r e n t ( m a ) ( m a ) figure 23 v cc undervoltage (-) vs temperature 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 v c c u n d e r v o l t a g e l o c k o u t + ( v ) temperature (c) max. typ. min. figure 24 v cc undervoltage (-) vs temperature 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature (c) max. typ. min. figure 25a output source current vs temperature figure 25b output source current vs voltage figure 26b output sink current vs voltage typ. min. typ. min. figure 26a output sink current vs temperature typ. min. typ. min. v c c u n d e r v o l t a g e l o c k o u t - ( v ) pdf created with pdffactory trial version www.pdffactory.com
irs2111(s)pbf www.irf.com 12 frequency (khz) figure 29. irs2111 t j vs. frequency (irfbc40) r gate = 15 ? ? ? ? ? , v cc = 15 v frequency (khz) figure 30. irs2111 t j vs. frequency (irfpc50) r gate = 10 ? ? ? ? ? , v cc = 15 v frequency (khz) figure 27. irs2111 t j vs. frequency (irfbc20) r gate = 33 ? ? ? ? ? , v cc = 15 v frequency (khz) figure 28. irs2111 t j vs. frequency (irfbc30) r gate = 22 ? ? ? ? ? , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature (c) 320 v 160 v 30 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature (c) 320 v 160 v 30 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature ( o c) 320 v 160 v 30v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature (c) 320 v 160 v 30 v
irs2111(s)pbf www.irf.com 13 frequency (khz) figure 33. irs2111s t j vs. frequency (irfbc40) r gate = 15 , v cc = 15 v frequency (khz) figure 34. irs2111s t j vs. frequency (irfpc50) r gate = 10 , v cc = 15 v frequency (khz) figure 31. irs2111s t j vs. frequency (irfbc20) r gate = 33 , v cc = 15 v frequency (khz) figure 32. irs2111s t j vs. frequency (irfbc30) r gate = 22 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature ( o c) 320 v 160 v 30 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature ( o c) 320 v 140 v 30 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature ( o c) 320 v 140 v 30 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 junction temperature ( o c) 320 v 140 v 30 v
irs2111(s)pbf www.irf.com 14 01-6014 01-3003 01 (ms-001ab) 8-lead pdip case outlines 01-6027 01-0021 11 (ms-012aa) 8-lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & toleranc ing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions no t to exc eed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions no t to exc eed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters in c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic
irs2111(s)pbf www.irf.com 15 carrier tape dimension for 8soicn code min max min max a 7 .9 0 8.1 0 0. 31 1 0 .3 18 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5 .4 5 5.5 5 0. 21 4 0 .2 18 e 6 .3 0 6.5 0 0. 24 8 0 .2 55 f 5 .1 0 5.3 0 0. 20 0 0 .2 08 g 1 .5 0 n/a 0.059 n/a h 1 .5 0 1.6 0 0. 05 9 0 .0 62 m etr ic im p erial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1 .9 5 2.4 5 0. 76 7 0 .0 96 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 m etr ic im p erial e f a c d g a b h n ot e : co ntrolling d imension in mm load ed ta pe feed direction a h f e g d b c tape & reel 8-lead soic
irs2111(s)pbf www.irf.com 16 order information 8-lead pdip irs2111pbf 8-lead soic irs2111spbf 8-lead soic tape & reel irs2111strpbf ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 leadfree part marking information lead free released non-lead free released part number date code irsxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code the soic-14 is msl3 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at www.irf.com data and specifications subject to change without notice. 12/4/2006 the soic-8 is msl2 qualified.

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